This invention relates to a differential amplifier circuit and semiconductor devices using such a differential amplifier circuit. More particularly, this invention relates to the circuit structure of a differential amplifier circuit capable of amplifying input voltages in the entire range of source voltage.
For microcomputers adapted to carry out digital processing, for example, logic circuits used to be formed by CMOS processes by which miniaturization is easier. In an interface, however, linear voltages are now frequently handled by using an analog-to-digital (A/D) converter, and MOS transistors are coming to be frequently used for forming linear circuits such as differential amplifiers.
FIG. 5 shows a prior art "n-type" differential amplifier circuit characterized as comprising a differential amplifier 1 using n-channel type MOS transistors (hereinafter referred to as "NMOS") 13 and 14 as a differential pair and a bias circuit 3 for providing a bias voltage to the differential amplifier 1. Explained more in detail, the differential amplifier 1 is of a structure similar to that of a bipolar transistor differential amplifier, comprising a differential pair of NMOS 13 and 14 to which input voltage is supplied respectively as inversion and non-inversion input voltage (V.sub.IN- and V.sub.IN+ at terminals IN- and IN+) through their gates, p-channel type MOS transistors (hereinafter referred to as "PMOS") 11 and 12 connected between a source voltage V.sub.DD and the drain respectively of the transistors 13 and 14 and forming a current mirror together, an NMOS 15 connecting together the sources of both transistors 13 and 14 to a reference voltage GND, and an inversion amplifier (or a buffer circuit) comprised of transistors 16 and 17, the gate and the source of transistor 16 being connected respectively to the junction between transistors 12 and 14 and to the source voltage V.sub.DD, and transistor 17 being connected in series between the drain of transistor 16 and the reference voltage GND. An output terminal (OUT) is connected to a junction between transistors 16 and 17. The gate and the drain of the PMOS 16 are connected through a phase-compensating capacitor C for reducing the gain of the amplifier during a high-frequency operation so as to prevent oscillations. The bias circuit 3 comprises an NMOS 31 (or a transistor diode) with its gate and drain connected together and a resistor 32 connected between the drain of the NMOS 31 and the source voltage V.sub.DD. The drain of the NMOS 31 is connected to the gates of the transistors 15 and 17.
To briefly explain the operation of the circuit shown in FIG. 5, the operating current of the differential amplifier 1 is determined by the voltage generated in the bias circuit 3 as the sum of the currents flowing through the NMOS 13 and 14. When V.sub.IN- and V.sub.IN+ are equal to each other, NMOS 13 and 14 are balanced, one half of the total operating current flowing through each of NMOS 13 and 14. When input voltage V.sub.IN+ becomes higher than input voltage V.sub.IN-, the current flowing through NMOS 13 becomes smaller and the voltage between its source and drain becomes larger. As a result, the gate voltage of PMOS 11 rises in order to reduce the current which flows to PMOS 11. Since this also reduces the current flowing to PMOS 12, the output voltage V.sub.OUT at the gate of PMOS 16 drops and the current flowing to PMOS 16 increases. As a result, it operates such that the output voltage V.sub.OUT will increase. When input voltage V.sub.IN+ becomes lower than input voltage V.sub.IN-, on the other hand, it operates such that the output voltage V.sub.OUT will decrease.
The transistor characteristic of NMOS is as schematically shown in FIG. 6, having a threshold value V.sub.th. Thus, if the voltage V.sub.gs between the gate and the source of transistor 13 or 14 of the differential pair 1 of FIG. 5 becomes lower than the threshold value V.sub.th, the current I.sub.d therethrough will drop nearly to zero. In other words, the differential pair 1 will cease to operate as described above or its frequency characteristic deteriorates substantially if the input voltage V.sub.IN+ or V.sub.IN- becomes lower than V.sub.th. Similarly, a so-called "p-type" differential amplifier, which uses PMOS for its differential pair, ceases to operate normally if a voltage greater than V.sub.DD -V.sub.th is inputted as input voltage.
Use has frequently been made of circuits as shown in FIG. 7 in order to address to the problems described above. The differential amplifier circuit shown in FIG. 7 is characterized by a parallel combination of a p-type differential amplifier 4 using PMOS for its differential pair and an n-type differential amplifier 1 (as described above with reference to FIG. 5). There is also provided a switching circuit 6 (controlled by a control signal CTL) for selecting the output from the appropriate one of the differential amplifiers 1 and 4 which will carry out the normal amplification operation in response to the input voltage (received through input terminals IN1 and IN2), such (received through input terminals IN1 and IN2), such that the range of acceptable input voltage is expanded.
Although a circuit of the type shown in FIG. 7 has the advantage of enlarging the range of acceptable input voltage, there are disadvantages in that two differential amplifiers, a switching circuit and a control unit therefor are required. As a result, both the total number of elements for the circuit and its area increase significantly, and this affects the unit price of the semiconductor device incorporating it. Moreover, it involves a difficult process of matching the characteristics of the differential amplifiers 1 and 4, as well as their offset voltages.